HD66740 Datasheet, PDF (12/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
Block Function Description
System Interface
The HD66740 has six types of system interfaces, and a clock-synchronized serial, an I2C bus interface, a
68-system 4-bit/8-bit bus, and a 80-system 4-bit/8-bit bus. The interface mode is selected by the IM2-0
pins.
The HD66740 has two 8-bit registers: an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as clear display, display control, and address information for the
display character generator RAM (CGRAM).
The DR temporarily stores data to be written into the CGRAM. Data written into the DR from the MPU is
automatically written into the CGRAM by internal operation. When address information is written into the
IR, data is read and then stored in the DR from the CGRAM by internal operation. Data is read through the
DR when reading from the RAM, and the first read data is invalid and the second and the following data are
normal. After reading, data in the CGRAM at the next address is sent to the DR for the next reading from
the MPU.
Execution time for instruction excluding clear display is 0 clock cycle and instructions can be written in
succession.
Table 3 Register Selection by RS and R/W Bits
R/W Bit RS Bit Operations
0
0
Write instructions to IR
1
0
-
0
1
DR write as an internal operation (DR to CGRAM)
1
1
DR read as an internal operation (CGRAM to DR)
Address Counter (AC)
The address counter (AC) assigns addresses to the CGRAM. When an address set instruction is written into
the IR, the address information is sent from the IR to the AC.
After writing into the CGRAM, the AC is automatically incremented by 1 (or decremented by 1). After
reading from the data, the RDM bit automatically updates or does not update the AC.
Character Generator RAM (CGRAM)
The CGRAM serves as a RAM to store 112 x 80-dot bit pattern data in the graphics display mode. Here,
display patterns are directly written into CGRAM. For details, see the Graphics Display section.
Timing Generator
The timing generator generates timing signals for the operation of internal circuits such as the CGRAM.
The RAM read timing for display and internal operation timing by MPU access are generated separately to
avoid interference with one another. This prevents flickering in areas other than the display area when
writing data to the CGRAM, for example.
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