HD66740 Datasheet, PDF (41/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
Parallel Data Transfer
8-bit Bus Interface
Setting the IM2/1/0 (interface mode) to the GND/Vcc/GND level allows E-clock-synchronized 8-bit
parallel data transfer. Setting the IM2/1/0 (interface mode) to the Vcc/Vcc/GND level allows 80-
system 8-bit parallel data transfer. When the number of buses or the mounting area is limited, use a 4-
bit bus interface or serial data transfer.
*Interface via I/O port
C0
C1
H8/325
C2
A0–A7
8
E/WR*
RS
R/W / RD* ^HD66740
(CS*)
DB0–DB7
Figure 17 Interface to 8-bit Microcomputer
4-bit Bus Interface
Setting the IM2/1/0 (interface mode) to the GND/Vcc/Vcc level allows E-clock-synchronized 4-bit
parallel data transfer using pins DB7-DB4. Setting the IM2/1/0 (interface mode) to the Vcc/Vcc/Vcc
level allows 80-system 4-bit parallel data transfer. The 8-bit instructions and RAM data are divided into
four upper/lower bits and the transfer starts from the upper four bits.
Note:
Transfer synchronization function for a 4-bit bus interface
The HD66740 supports the transfer synchronization function which resets the upper/lower
counter to count upper/lower 4-bit data transfer in the 4-bit bus interface. Noise causing
transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by
consecutively writing a 0000 instruction four times. The next transfer starts from the upper
four bits. Executing synchronization function periodically can recover any runaway in the
display system.
RS
R/W
E
DB7–
DB4
Upper/
lower
"0000" "0000" "0000"
(1)
(2)
(3)
"0000"
(4)
Upper
Lower
(4-bit transfer synchronization)
Figure 18 4-bit Transfer Synchronization
41