HD66740 Datasheet, PDF (37/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
Serial Data Transfer (Clock synchronized serial interface)
Setting the IM1 and IM2 pins (interface mode pins) to the GND level allows standard clock-synchronized
serial data transfer, using the chip select line (CS*), serial data line (SDA), and serial transfer clock line
(SCL). For a serial interface, the IM0/ID pin function uses an ID pin.
The HD66740 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It
ends serial data transfer at the rising edge of CS* input.
The HD66740 is selected when the 6-bit chip address in the start byte transferred from the transmitting
device matches the 6-bit device identification code assigned to the HD66740. The HD66740, when
selected, receives the subsequent data string. The least significant bit of the identification code can be
determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be
assigned to a single HD66740 because the seventh bit of the start byte is used as a register select bit (RS):
that is, when RS = 0, an instruction can be issued, and when RS = 1, data can be written to or read from
RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit) as shown in table
16.
After receiving the start byte, the HD66740 receives or transmits the subsequent data byte-by-byte. The
data is transferred with the MSB first.
Two bytes of RAM read data after the start byte are invalid. The HD66740 starts to read correct RAM
data from the third byte.
Table 15 Start Byte Format
Transfer Bit
S
1
2
3
4
5
6
7
8
Start byte format
Transfer start Device ID code
RS R/W
0
1
1
1
0
ID
Note: ID bit is selected by the IM0/ID pin.
Table 16 RS and R/W Bit Function
RS R/W Function
0
0
Writes instruction
0
1
-
1
0
Writes RAM data
1
1
Reads RAM data
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