HD66740 Datasheet, PDF (34/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
Table 14 Instruction List (cont)
Register
Name
Code
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Execu-
tion
Cycle
LCD-driving-
0001 110
pattern control
0 DCC B/C Selects the boosting cycle 0
(DCC) or LCD drive AC
waveform (B/C)
LCD-driving-
0 0 0 1 1 1 1 NW2 NW1 NW0 Sets the number of n-raster- 0
waveform control
rows (NW2–0) in C-pattern
AC drive.
EOR NW4 NW3 Sets the EOR output (EOR) 0
or the number of n-raster-
rows (NW4–3) in C-pattern
AC drive.
RAM address set 0 0 1 0 1
(upper bits)
AD10–6
(upper bits)
Initially sets the upper
0
addresses of the RAM to the
address counter (AC).
RAM address set 0 0 1 1
(lower bits)
AD5-0
(lower bits)
Initially sets the lower
0
addresses of the RAM to the
AC.
Write data to RAM 0 1
Write data
Writes data to CGRAM.
0
Read data from 1 1
RAM
Read data
Reads data from CGRAM. 0
Notes: 1. The upper column of each register can be set when SW = 0. The lower column can be set
when SW = 1.
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