GS81313LT18 Datasheet, PDF (9/29 Pages) GSI Technology – 144Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

GS81313LT18/36GK-833/714/625
DQ ODT Control
A robust methodology has been developed for these devices for controlling when DQ ODT is enabled and disabled during
Write-to-Read and Read-to-Write transitions. Specifically, the methodology can ensure that the DQ bus is never pulled to V_DDQ/2
by the SRAM ODT and/or by the controller ODT during the transitions (or at any other time). Such a condition is best avoided,
because if an input signal is pulled to V_DDQ/2 (i.e. to V_REF - the switch point of the diff-amp receiver), it could cause the receiver
to enter a meta-stable state and consume more power than it normally would otherwise. This could result in the device’s operating
currents being higher than specified.
The fundamental concept of the methodology is - both the SRAM and the controller drive the DQ bus Low (with DQ ODT
disabled) at all times except:
1. When a particular device is driving the DQ bus with valid data, and
2. From shortly before to shortly after a particular device is receiving valid data on the DQ bus, during which time the receiving
device enables its DQ ODT.
And, during Write-to-Read and Read-to-Write transitions, each device enables and disables its DQ ODT while the other device is
driving DQ Low, thereby ensuring that the DQ bus is never pulled to V_DDQ/2.
Note: This methodology also reduces power consumption, since there will be no DC current through either device’s DQs when
both devices are driving Low.
In order for this methodology to work as described, the controller must have the ability to:
1. Place the SRAM into “DQ Drive Low Mode” at the appropriate times (i.e. before and after the SRAM drives read data), and
2. Place the SRAM into “DQ ODT Mode” at the appropriate times (i.e. before, during, and after the SRAM receives write data).
That ability is provided via the existing R/W control pin.
When the SRAM samples R/W High (regardless of the state of LD), it disables its DQ ODT, and drives the DQ bus Low except
while driving valid read data in response to Read operations.
When the SRAM samples R/W Low (regardless of the state of LD), it disables its DQ drivers, and enables its DQ ODT.
Note that NOPs initiated with R/W High and LD High are referred to as “NOPr” operations.
Note that NOPs initiated with R/W Low and LD High are referred to as “NOPw” operations.
This extended definition of the R/W control pin allows the controller to:
• Place the SRAM in DQ ODT Mode, via NOPw operations, before initiating Write operations.
• Keep the SRAM in DQ ODT Mode, via NOPw operations, after initiating Write operations.
• Place the SRAM in DQ Drive Low Mode, via NOPr operations, before initiating Read operations.
• Keep the SRAM in DQ Drive Low Mode, via NOPr operations, after initiating Read operations.
Operation Sequence Rule
Because of how R/W is used to control the state of the DQs, when a Read operation is initiated in cycle “n”, R/W must be driven
“high” in cycle “n+1” (i.e. a Read operation must always be followed by a Read or NOPr operation) in order to ensure that the DQ
state in cycle “n+3” is “Read Data”.
Rev: 1.13 7/2016
9/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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