GS81313LT18 Datasheet, PDF (8/29 Pages) GSI Technology – 144Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

GS81313LT18/36GK-833/714/625
Clock Truth Table
SA
LD
R/W
Current Operation
DQ (D)
DQ (Q)
CK
CK
CK
KD
KD
CQ
CQ
(t_n)
(t_n)
(t_n)
(t_n)
(t_n)
(t_n+½)
(t_n+3)
(t_n+3½)
V
1
X
NOP
X
X
Hi-Z / other
V
0
0
Write
D1
D2
Hi-Z / other
V
0
1
Read
X
X
Q1
Q2
Notes:
1. 1 = High 0 = Low; V = Valid; X = don’t care.
2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
4. When DQ ODT is disabled, DQ pins are tri-stated for one cycle in response to NOP and Write commands, 3 cycles after the command is
sampled. See the DQ ODT Control section below for how the state of the DQ pins is controlled when DQ ODT is enabled.
Rev: 1.13 7/2016
8/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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