GS81313LT18 Datasheet, PDF (25/29 Pages) GSI Technology – 144Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

GS81313LT18/36GK-833/714/625
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the
Shift-DR state.
The ID Register is 32 bits wide, and is encoded as follows:
See BSDL Model
(31:12)
XXXX XXXX XXXX XXXX XXXX
GSI ID
(11:1)
0001 1011 001
Start Bit
(0)
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 129 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (DQ, QVLD, CQ, CQ) are driven
directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST
instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state
does not appear at the output pins until the TAP Controller has reached the Update-DR state.
The value captured in the boundary scan register for NU pins is determined by the external pin state. The value captured in the
boundary scan register for NC pins is 0 regardless of the external pin state. The value captured in the Internal Cell (Bit 129) is 1.
Output Driver State During EXTEST
EXTEST allows the Internal Cell (Bit 129) in the Boundary Scan Register to control the state of DQ drivers. That is, when Bit 129
= 1, DQ drivers are enabled (i.e., driving High or Low), and when Bit 129 = 0, DQ drivers are disabled (i.e., forced to High-Z
state). See the Boundary Scan Register section for more information.
ODT State During EXTEST and SAMPLE-Z
ODT on all inputs is disabled during EXTEST and SAMPLE-Z.
Rev: 1.13 7/2016
25/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology