GS81313LT18 Datasheet, PDF (24/29 Pages) GSI Technology – 144Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

GS81313LT18/36GK-833/714/625
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction
(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
000
001
010
011
100
101
110
111
Instruction
EXTEST
IDCODE
SAMPLE-Z
PRIVATE
SAMPLE
PRIVATE
PRIVATE
BYPASS
Description
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with output signals (DQ, QVLD,
CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan Register
contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.
Also disables all ODT.
See the Boundary Scan Register description for more information.
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the
TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the
TAP Controller is in the Shift-DR state.
See the ID Register description for more information.
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also disables all ODT.
Also forces DQ output drivers to a High-Z state.
See the Boundary Scan Register description for more information.
Reserved for manufacturer use only.
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
Reserved for manufacturer use only.
Reserved for manufacturer use only.
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and
inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Bypass Register description for more information.
Rev: 1.13 7/2016
24/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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