GS81313LT18 Datasheet, PDF (18/29 Pages) GSI Technology – 144Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

GS81313LT18/36GK-833/714/625
AC Timing Specifications (independent of device speed grade)
Parameter
Symbol
Min
Max
Units Notes
Input Clock Timing
Clk High Pulse Width
t_KHKL
0.45
—
cycles 1
Clk Low Pulse Width
t_KLKH
0.45
—
cycles 1
Clk High to Clk High
t_KHKH
0.45
0.55
cycles 2
Clk High to Write Data Clk High
t_KHKDH
-250
+250
ps
3
Clk Cycle-to-Cycle Jitter
t_KJITcc
—
60
ps 1,4,5
PLL Lock Time
t_Klock
65,536
—
cycles 6
Clk Static to PLL Reset
t_Kreset
30
—
ns 7,12
Output Timing
Clk High to Output Valid / Hold
t_KHQV/X
+0.4
+1.2
ns
8
Clk High to Output State Transition
t_KHDQT
+0.4
+1.2
ns
8
Clk High to Echo Clock High
t_KHCQH
+0.4
+1.2
ns
9
Echo Clk High to Output Valid / Hold
t_CQHQV/X
-120
+120
ps 10,12
Echo Clk High to Echo Clock High
t_CQHCQH
0.5*t_KHKH (nom) - 50
0.5*t_KHKH (nom) + 50
ps 11,12
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter specifiesCK CK and KD KD requirements.
3. Parameter specifies CK KD and CK KD requirements.
4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge). 
As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to  30ps. 
And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to  15ps.
5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed
grade, t_KHKH (min) of that speed grade must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For
example, if the actual C2C Jitter is 100ps, then t_KHKH (min) for the -714 speed grade is derated to 1.42ns (1.4ns + 0.5*(100ps - 60ps)).
6. V_DD slew rate must be < 0.1V DC per 50ns for PLL lock retention. PLL lock time begins once V_DD and input clock are stable.
7. Parameter applies to CK.
8. Parameters apply to DQ, and are referenced to CK.
9. Parameter specifies CK CQ timing.
10. Parameters apply to DQ, QVLD and are referenced to CQ & CQ.
11. Parameter specifies CQ CQ timing. t_KHKH (nom) is the nominal input clock cycle time applied to the device.
12. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.13 7/2016
18/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology