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GS81313LT18 Datasheet, PDF (5/29 Pages) GSI Technology – 144Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™ | |||
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GS81313LT18/36GK-833/714/625
Symbol
PZT[1:0]
VDD
VDDQ
VREF
VSS
TCK
TMS
TDI
TDO
MCH
MCL
NC
NUI
NUIO
Description
ODT Configuration Select â Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Core Power Supply
I/O Power Supply
Input Reference Voltage â Input buffer reference voltage.
Ground
JTAG Clock â Weakly pulled Low internally.
JTAG Mode Select â Weakly pulled High internally.
JTAG Data Input â Weakly pulled High internally.
JTAG Data Output
Must Connect High â May be tied to VDDQ directly or via a 1kï resistor.
Must Connect Low â May be tied to VSS directly or via a 1kï resistor.
No Connect â There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input â There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Input/Output â There is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied/driven Low. They should not be tied/driven High.
Type
Input
â
â
â
â
Input
Input
Input
Output
Input
Input
â
Input
I/O
Rev: 1.13 7/2016
5/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
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