MC9S08SH32 Datasheet, PDF (81/328 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output Control
6.6.1 Port A Registers
Port A is controlled by the registers listed below.
The pins PTA4 and PTA5 are unique. PTA4 is output-only, so the control bits for the input function will
not have any effect on this pin. PTA5, when configured as an output, is open drain.
NOTE
This PTA5 pin does not contain a clamp diode to V_DD and should not be
driven above V_DD.
When the internal pullup device is enabled on PTA5 when used as an input
or open drain output the voltage measured on PTA5 will not be pulled to
V_DD. The internal gates connected to this pin are pulled to V_DD. If the PTA5
pin is required to drive to a V_DD level an external pullup should be used.
6.6.1.1 Port A Data Register (PTAD)
7
R
PTAD7
W
6
PTAD6
5
PTAD5
4
PTAD4¹
3
PTAD3
2
PTAD2
1
PTAD1
Reset:
0
0
0
0
0
0
0
Figure 6-3. Port A Data Register (PTAD)
1 _{Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.}
0
PTAD0
0
Table 6-2. PTAD Register Field Descriptions
Field
Description
7:0
PTAD[7:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
81
PRELIMINARY