MC9S08SH32 Datasheet, PDF (301/328 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.9 Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
1
P
Internal reference frequency — factory trimmed at V_DD
= 5 V and temperature = 25°C
f_{int_ft}
—
31.25
—
kHz
2 T _{Internal reference frequency — untrimmed}¹
f_{int_ut}
25
36
41.66
kHz
3 P Internal reference frequency — trimmed
f_{int_t}
31.25
—
39.0625 kHz
4 D Internal reference startup time
t_irefst
—
55
100
μs
5
—
DCO output frequency range — untrimmed¹ value
provided for reference: f_{dco_ut} = 1024 x f_{int_ut}
f_{dco_ut}
25.6
36.86
42.66
MHz
6 D DCO output frequency range — trimmed
f_{dco_t}
32
—
40
MHz
7
D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δf_{dco_res_t}
—
± 0.1
± 0.2
%f_dco
8
D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Δf_{dco_res_t}
—
± 0.2
± 0.4
%f_dco
9
D
Total deviation of trimmed DCO output frequency over
voltage and temperature
Δf_{dco_t}
—
+ 0.5
– 1.0
±2
%f_dco
Total deviation of trimmed DCO output frequency over
10 D _{fixed voltage and temperature range of 0°C to 70 °C}
Δf_{dco_t}
—
± 0.5
±1
%f_dco
11 D _{FLL acquisition time} ²
t_acquire
1
ms
12 D _{DCO output clock long term jitter (over 2 ms interval)} ³
C_Jitter
—
0.02
0.2
%f_dco
1 _{TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing}
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
3 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a
given interval.
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
301
PRELIMINARY