MC9S08SH32 Datasheet, PDF (186/328 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Modulo Timer (S08MTIMV1)
12.1.4 Block Diagram
The block diagram for the modulo timer module is shown Figure 12-2.
BUSCLK
XCLK
TCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALE
AND SELECT
DIVIDE BY
8-BIT COUNTER
(MTIMCNT)
TRST
TSTP
CLKS
PS
MTIM
INTERRUPT
REQUEST
TOF
TOIE
8-BIT COMPARATOR
8-BIT MODULO
(MTIMMOD)
Figure 12-2. Modulo Timer (MTIM) Block Diagram
12.2 External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in Table 12-1.
Table 12-1. Signal Properties
Signal
Function
I/O
TCLK
External clock source input into MTIM
I
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter must
be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for
the pin location and priority of this function.
MC9S08SH32 Series Data Sheet, Rev. 2
186
Freescale Semiconductor
PRELIMINARY