MC9S08SH32 Datasheet, PDF (78/328 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output Control
6.4 Pin Interrupts
Port A[3:0] and port B[3:0] pins can be configured as external interrupt inputs and as an external means of
waking the MCU from stop3 or wait low-power modes.
The block diagram for the pin interrupts is shown Figure 6-2.
PIxn
1
0S
PTxPS0
PTxES0
1
PIxn
0 _{S PTxPSn}
PTxESn
V_DD
D ^CLR Q
CK
PTxACK
RESET
BUSCLK
PTxIF
SYNCHRONIZER
PTxMOD
PORT
INTERRUPT FF
STOP ^{STOP BYPASS}
PTxIE
PTx
INTERRUPT
REQUEST
Figure 6-2. Pin Interrupt Block Diagram
Writing to the PTxPSn bits in the port interrupt pin enable register (PTxPS) independently enables or
disables each port pin interrupt. Each port can be configured as edge sensitive or edge and level sensitive
based on the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can
be software programmed to be either falling or rising; the level can be either low or high. The polarity of
the edge or edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select
register (PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled pin interrupt inputs must be
at the deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic
1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle.
A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1
during the next cycle.
6.4.1 Edge-Only Sensitivity
A valid edge on an enabled pin interrupt sets PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request is presented to the CPU. To clear PTxIF, write a 1 to PTxACK in PTxSC.
NOTE
If a pin is enabled for interrupt on edge-sensitive only, a falling (or rising)
edge on the pin does not latch an interrupt request if another pin interrupt is
already asserted.
To prevent losing an interrupt request on one pin because another pin is
asserted, software can disable the asserted pin interrupt while having the
unasserted pin interrupt enabled. The asserted status of a pin is reflected by
its associated I/O general purpose data register.
MC9S08SH32 Series Data Sheet, Rev. 2
78
Freescale Semiconductor
PRELIMINARY