MC68HC908JL3 Datasheet, PDF (73/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
7.3.1 Entering Monitor Mode
Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR and will allow communication at 9600 baud provided one of the following sets
of conditions is met:
1. If IRQ = V_TST:
– Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL)
– PTB3 = low
2. If IRQ = V_TST:
– Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL)
– PTB3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
– Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC)
– IRQ = V_DD
Table 7-1. Monitor Mode Entry Requirements and Options
IRQ
OSC1 Frequency
Bus
Frequency
Comments
V_TST(2)
V_TST
V_DD
V_DD
X
0011
X
1011
BLANK
(contain
$FF)
NOT
BLANK
XXX1
XXXX
4.9152 MHz
9.8304 MHz
9.8304 MHz
At desired
frequency
2.4576 MHz
(OSC1 ÷ 2)
2.4576 MHz
(OSC1 ÷ 4)
2.4576 MHz
(OSC1 ÷ 4)
OSC1 ÷ 4
High-voltage entry to monitor
mode.⁽³⁾
9600 baud communication on
PTB0. COP disabled.
Low-voltage entry to monitor
mode.⁽⁴⁾
9600 baud communication on
PTB0. COP disabled.
Enters User mode.
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using V_TST for monitor mode entry.
The OSC1 clock must be 50% duty cycle for this condition.
2. See Table 16-4. DC Electrical Characteristics (5V) for V_TST voltage level requirements.
3. For IRQ = V_TST:
MC68HRC908JL3E/JK3E/JK1E — clock must be EXT OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
4. For IRQ = V_DD:
MC68HRC908JL3E/JK3E/JK1E — clock must be RC OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
If V_TST is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus
frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with V_TST applied to IRQ upon
monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to
OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if V_TST is applied to IRQ. In this event, the OSCOUT frequency is equal to the
2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
73