MC68HC908JL3 Datasheet, PDF (128/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low Voltage Inhibit (LVI)
14.4 LVI Control Register (CONFIG2/CONFIG1)
The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2.
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IRQPUD
R
R
LVIT1
LVIT0
R
R
R
Write:
Reset: 0
0
0
Not affected Not affected
0
0
0
POR: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 14-2. Configuration Register 2 (CONFIG2)
Address: $001F
Bit 7
6
Read:
COPRS
R
Write:
5
4
3
2
1
R
LVID
R
SSREC STOP
Reset: 0
0
0
0
0
0
0
R
= Reserved
Figure 14-3. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
LVID — Low Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection
These two bits determine at which level of V_DD the LVI module will come into action. LVIT1 and LVIT0
are cleared by a Power-On Reset only.
LVIT1
0
0
1
1
LVIT0
0
1
0
1
Trip Voltage⁽¹⁾
V_LVR3 (2.4V)
V_LVR3 (2.4V)
V_LVR5 (4.0V)
Reserved
1. See Chapter 16 Electrical Specifications for full parameters.
Comments
For V_DD=3V operation
For V_DD=3V operation
For V_DD=5V operation
14.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power-consumption standby modes.
14.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
14.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
MC68HC908JL3E Family Data Sheet, Rev. 4
128
Freescale Semiconductor