MC68HC908JL3 Datasheet, PDF (27/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Random-Access Memory (RAM)
Vector Priority
Lowest
Highest
Table 2-1. Vector Addresses
INT Flag
—
IF15
IF14
IF13
↓
IF6
IF5
IF4
IF3
IF2
IF1
—
—
Address
$FFD0
↓
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
—
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
—
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
Not Used
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
Keyboard Vector (High)
Keyboard Vector (Low)
Not Used
TIM Overflow Vector (High)
TIM Overflow Vector (Low)
TIM Channel 1 Vector (High)
TIM Channel 1 Vector (Low)
TIM Channel 0 Vector (High)
TIM Channel 0 Vector (Low)
Not Used
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
2.4 Random-Access Memory (RAM)
Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero
RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
27