MC68HC908JL3 Datasheet, PDF (130/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Break Module (BREAK)
Addr.
Register Name
$FE00
Read:
Break Status Register
(BSR)
Write:
Reset:
$FE03
Break Flag Control ^Read:
Register Write:
(BFCR) _Reset:
$FE0C
Break Address High ^Read:
Register Write:
(BRKH) _Reset:
$FE0D
Break Address low ^Read:
Register Write:
(BRKL) _Reset:
$FE0E
Break Status and Control ^Read:
Register Write:
(BRKSCR) _Reset:
Note: Writing a 0 clears SBSW.
Bit 7
R
BCFE
0
Bit15
0
Bit7
0
BRKE
0
6
5
R
R
R
R
Bit14
Bit13
0
0
Bit6
Bit5
0
0
0
BRKA
0
0
= Unimplemented
4
3
2
1
Bit 0
SBSW
R
R
R
R
See note
0
R
R
R
R
R
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R = Reserved
Figure 15-2. Break I/O Register Summary
15.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR) and see the Break Interrupts
subsection for each module.)
15.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
15.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_TST is present on the RST pin.
MC68HC908JL3E Family Data Sheet, Rev. 4
130
Freescale Semiconductor