MC68HC908JL3 Datasheet, PDF (169/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles instead of a
4096 × 2OSCOUT cycle delay.
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
B.5.3 Mask Option Register 2 (MOR2)
Address: $001E
Bit 7
6
Read: IRQPUD
0
5
4
3
2
0
LVIT1
LVIT0
0
1
Bit 0
0
0
Write:
Reset: 0
0
0
Not
Not
affected affected
0
0
0
POR: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-2. Mask Option Register 2 (MOR2)
IRQPUD — IRQ Pin Pull-up control bit
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and V_DD
LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits
Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI)
B.6 Monitor ROM
The monitor program (monitor ROM: $FE10–$FFCF) on the MC68H(R)C08JL3E/JK3E is for device
testing only. $FC00–$FDFF are unused.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
169