MC68HC908JL3 Datasheet, PDF (53/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Reset and System Initialization
IRST
RST
2OSCOUT
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
Figure 5-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 5-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
5.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur.
At power-on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive 2OSCOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 2OSCOUT cycles to allow
stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
53