MC68HC908JL3 Datasheet, PDF (111/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port D
10.4.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a one to a
DDRD bit enables the output buffer for the corresponding port D pin; a zero disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
Figure 10-10. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 10-11 shows the
port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDPU[6:7]
5k
PTDx
READ PTD ($0003)
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
Figure 10-11. Port D I/O Circuit
When DDRDx is a 1, reading address $0003 reads the PTDx data latch. When DDRDx is a 0, reading
address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit. Table 10-4 summarizes the operation of the port D pins.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
111