K51P81M100SF2 Datasheet, PDF (68/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Revision History
VDD
1
VSS
2
USB0_DP
3
USB0_DM
4
VOUT33
5
VREGIN
6
ADC0_DP1/OP0_DP0
7
ADC0_DM1/OP0_DM0
8
ADC1_DP1/OP1_DP0/OP1_DM1
9
ADC1_DM1/OP1_DM0
10
PGA0_DP/ADC0_DP0/ADC1_DP3
11
PGA0_DM/ADC0_DM0/ADC1_DM3
12
PGA1_DP/ADC1_DP0/ADC0_DP3
13
PGA1_DM/ADC1_DM0/ADC0_DM3
14
VDDA
15
VREFH
16
VREFL
17
VSSA
18
ADC1_SE16/OP1_OUT/
ADC0_SE22/OP0_DP2/OP1_DP2
19
ADC0_SE16/OP0_OUT/CMP1_IN2/
20
ADC0_SE21/OP0_DP1/OP1_DP1
60
VLL3
59
VSS
58
PTC3
57
PTC2
56
PTC1
55
PTC0
54
PTB19
53
PTB18
52
PTB17
51
PTB16
50
PTB11
49
PTB10
48
PTB9
47
PTB8
46
PTB3
45
PTB2
44
PTB1
43
PTB0
42
RESET_b
41
PTA19
Figure 28. K51 80 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
68
Preliminary
Freescale Semiconductor, Inc.