K51P81M100SF2 Datasheet, PDF (16/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

General
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled. Code executing from flash.
7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled.
9. Includes 32kHz oscillator current and RTC operation.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled, USB regulator disabled
• No GPIOs toggled
• Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16
Preliminary
Freescale Semiconductor, Inc.