K51P81M100SF2 Datasheet, PDF (58/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 44. Slave mode DSPI timing (high-speed mode) (continued)
Num
DS11
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
Max.
Unit
—
TBD
ns
0
—
ns
2
—
ns
7
—
ns
—
14
ns
—
14
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 25. DSPI classic SPI timing — slave mode
6.8.6 _I²_{C switching specifications}
See General switching specifications.
6.8.7 UART switching specifications
See General switching specifications.
6.8.8 _I²_{S switching specifications}
This section provides the AC timings for the I²S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
58
Preliminary
Freescale Semiconductor, Inc.