K51P81M100SF2 Datasheet, PDF (35/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

6.4.2
Peripheral operating requirements and behaviors
EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
EP1
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Description
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Min.
2.7
—
—
2 x t_{EZP_CK}
5
5
2
5
—
0
—
Max.
3.6
f_SYS/2
f_SYS/8
—
—
—
—
—
12
—
12
Unit
V
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP7
EP8
EP5
EP6
Figure 10. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
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