K51P81M100SF2 Datasheet, PDF (59/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 45. _I²_{S master mode timing}
Num
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
Description
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
Min.
2.7
2 x t_SYS
45%
5 x t_SYS
45%
—
-2.5
—
-3
20
0
Max.
3.6
55%
—
55%
15
—
15
—
—
—
Unit
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Num
S11
Figure 26. I²S timing — master mode
Table 46. _I²_{S slave mode timing}
Description
Operating voltage
I2S_BCLK cycle time (input)
Min.
2.7
8 x t_SYS
Table continues on the next page...
Max.
3.6
—
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
Unit
V
ns
59