K51P81M100SF2 Datasheet, PDF (65/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Pinout
81 80 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQF
BGA P
• 35 PTA2
JTAG_TDO/ TSI0_CH3 PTA2
TRACE_SW
O/EZP_DO
UART0_TX FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SW
O
• 36 PTA3
JTAG_TMS/ TSI0_CH4 PTA3
SWD_DIO
UART0_RT FTM0_CH0
S_b
JTAG_TMS/
SWD_DIO
• 37 PTA4
NMI_b/ TSI0_CH5 PTA4
EZP_CS_b
FTM0_CH1
NMI_b
EZP_CS_b
• 38 VDD
VDD
VDD
• 39 VSS
VSS
VSS
• 40 PTA18
EXTAL
EXTAL
PTA18
FTM0_FLT2 FTM_CLKIN
0
• 41 PTA19
XTAL
XTAL
PTA19
FTM1_FLT0 FTM_CLKIN
1
LPT0_ALT1
• 42 RESET_b RESET_b RESET_b
• 43 PTB0
LCD_P0/ LCD_P0/ PTB0
ADC0_SE8/ ADC0_SE8/
ADC1_SE8/ ADC1_SE8/
TSI0_CH0 TSI0_CH0
I2C0_SCL FTM1_CH0
FTM1_QD_ LCD_P0
PHA
• 44 PTB1
LCD_P1/ LCD_P1/ PTB1
ADC0_SE9/ ADC0_SE9/
ADC1_SE9/ ADC1_SE9/
TSI0_CH6 TSI0_CH6
I2C0_SDA FTM1_CH1
FTM1_QD_ LCD_P1
PHB
• 45 PTB2
LCD_P2/ LCD_P2/ PTB2
ADC0_SE1 ADC0_SE1
2/TSI0_CH7 2/TSI0_CH7
I2C0_SCL UART0_RT
S_b
FTM0_FLT3 LCD_P2
• 46 PTB3
LCD_P3/ LCD_P3/ PTB3
ADC0_SE1 ADC0_SE1
3/TSI0_CH8 3/TSI0_CH8
I2C0_SDA UART0_CT
S_b
FTM0_FLT0 LCD_P3
• 47 PTB8
LCD_P8 LCD_P8 PTB8
UART3_RT
S_b
LCD_P8
• 48 PTB9
LCD_P9 LCD_P9 PTB9
SPI1_PCS1 UART3_CT
S_b
LCD_P9
• 49 PTB10
LCD_P10/ LCD_P10/ PTB10
ADC1_SE1 ADC1_SE1
4
4
SPI1_PCS0 UART3_RX
FTM0_FLT1 LCD_P10
• 50 PTB11
LCD_P11/ LCD_P11/ PTB11
ADC1_SE1 ADC1_SE1
5
5
SPI1_SCK UART3_TX
FTM0_FLT2 LCD_P11
• 51 PTB16
LCD_P12/ LCD_P12/ PTB16
TSI0_CH9 TSI0_CH9
SPI1_SOUT UART0_RX
EWM_IN LCD_P12
• 52 PTB17
LCD_P13/ LCD_P13/ PTB17
TSI0_CH10 TSI0_CH10
SPI1_SIN UART0_TX
EWM_OUT LCD_P13
_b
• 53 PTB18
LCD_P14/ LCD_P14/ PTB18
TSI0_CH11 TSI0_CH11
FTM2_CH0 I2S0_TX_B
CLK
FTM2_QD_ LCD_P14
PHA
• 54 PTB19
LCD_P15/ LCD_P15/ PTB19
TSI0_CH12 TSI0_CH12
FTM2_CH1 I2S0_TX_F
S
FTM2_QD_ LCD_P15
PHB
• 55 PTC0
LCD_P20/ LCD_P20/ PTC0
ADC0_SE1 ADC0_SE1
SPI0_PCS4 PDB0_EXT I2S0_TXD
RG
LCD_P20
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
65