K51P81M100SF2 Datasheet, PDF (66/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Pinout
81 80 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQF
BGA P
4/
4/
TSI0_CH13 TSI0_CH13
• 56 PTC1
LCD_P21/ LCD_P21/ PTC1
ADC0_SE1 ADC0_SE1
5/
5/
TSI0_CH14 TSI0_CH14
SPI0_PCS3 UART1_RT FTM0_CH0
S_b
LCD_P21
• 57 PTC2
LCD_P22/ LCD_P22/ PTC2
ADC0_SE4 ADC0_SE4
b/
b/
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
SPI0_PCS2 UART1_CT FTM0_CH1
S_b
LCD_P22
• 58 PTC3
LCD_P23/ LCD_P23/ PTC3
CMP1_IN1 CMP1_IN1
SPI0_PCS1 UART1_RX FTM0_CH2
LCD_P23
• 59 VSS
VSS
VSS
• 60 VLL3
VLL3
VLL3
• 61 VLL2
VLL2
VLL2
• 62 VLL1
VLL1
VLL1
• 63 VCAP2 VCAP2 VCAP2
• 64 VCAP1 VCAP1 VCAP1
• 65 PTC4
LCD_P24 LCD_P24 PTC4
SPI0_PCS0 UART1_TX FTM0_CH3
CMP1_OUT LCD_P24
• 66 PTC5
LCD_P25 LCD_P25 PTC5
SPI0_SCK
LPT0_ALT2
CMP0_OUT LCD_P25
• 67 PTC6
LCD_P26/ LCD_P26/ PTC6
CMP0_IN0 CMP0_IN0
SPI0_SOUT PDB0_EXT
RG
LCD_P26
• 68 PTC7
LCD_P27/ LCD_P27/ PTC7
CMP0_IN1 CMP0_IN1
SPI0_SIN
LCD_P27
• 69 PTC8
LCD_P28/ LCD_P28/ PTC8
ADC1_SE4 ADC1_SE4
b/
b/
CMP0_IN2 CMP0_IN2
I2S0_MCLK I2S0_CLKIN
LCD_P28
• 70 PTC9
LCD_P29/ LCD_P29/ PTC9
ADC1_SE5 ADC1_SE5
b/
b/
CMP0_IN3 CMP0_IN3
I2S0_RX_B
CLK
FTM2_FLT0 LCD_P29
• 71 PTC10
LCD_P30/
ADC1_SE6
b/
CMP0_IN4
LCD_P30/
ADC1_SE6
b/
CMP0_IN4
PTC10
I2C1_SCL
I2S0_RX_F
S
LCD_P30
• 72 PTC11
LCD_P31/ LCD_P31/ PTC11
ADC1_SE7 ADC1_SE7
b
b
I2C1_SDA
I2S0_RXD
LCD_P31
• 73 PTD0
LCD_P40 LCD_P40 PTD0
SPI0_PCS0 UART2_RT
S_b
LCD_P40
• 74 PTD1
LCD_P41/ LCD_P41/ PTD1
ADC0_SE5 ADC0_SE5
b
b
SPI0_SCK UART2_CT
S_b
LCD_P41
• 75 PTD2
LCD_P42 LCD_P42 PTD2
SPI0_SOUT UART2_RX
LCD_P42
• 76 PTD3
LCD_P43 LCD_P43 PTD3
SPI0_SIN UART2_TX
LCD_P43
EzPort
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
66
Preliminary
Freescale Semiconductor, Inc.