K51P81M100SF2 Datasheet, PDF (60/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 46. _I²_{S slave mode timing (continued)}
Num
S12
S13
S14
S15
S16
S17
S18
Description
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
Min.
45%
10
3
—
0
10
2
Max.
55%
—
—
20
—
—
—
Unit
MCLK period
ns
ns
ns
ns
ns
ns
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
S11
S12
S15
S13
S15
S12
S15
S16
S17
S18
S16
S14
S16
Figure 27. I²S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 47. TSI electrical specifications
Symbol
V_DDTSI
C_ELE
f_REFmax
f_ELEmax
C_REF
V_DELTA
Description
Operating voltage
Target electrode capacitance range
Reference oscillator frequency
Electrode oscillator frequency
Internal reference capacitor
Oscillator delta voltage
Min.
1.71
1
—
—
TBD
TBD
Typ.
—
20
5.5
0.5
1
600
Max.
3.6
500
TBD
TBD
TBD
TBD
Table continues on the next page...
Unit
V
pF
MHz
MHz
pF
mV
Notes
1
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
60
Preliminary
Freescale Semiconductor, Inc.