K60P104M100SF2 Datasheet, PDF (61/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet

Pinout
8 Pinout
8.1 K60 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
100 Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QFP
y _{1 ADC1_SE4a ADC1_SE4a PTE0}
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA
2 ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0
I2C1_SCL
r _{3 ADC1_SE6a ADC1_SE6a PTE2}
SPI1_SCK
UART1_CTS_ SDHC0_DCLK
b
a _{4 ADC1_SE7a ADC1_SE7a PTE3}
SPI1_SIN
UART1_RTS_ SDHC0_CMD
b
in ^{5 DISABLED}
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
6 DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
7 DISABLED
PTE6
SPI1_PCS3 UART3_CTS_ I2S0_MCLK
b
I2S0_CLKIN
8 VDD
VDD
lim ^{9 VSS}
VSS
10 USB0_DP USB0_DP
11 USB0_DM USB0_DM
12 VOUT33
VOUT33
e _{13 VREGIN}
VREGIN
r ^{14 ADC0_DP1 ADC0_DP1}
15 ADC0_DM1 ADC0_DM1
P ^{16 ADC1_DP1 ADC1_DP1}
EzPort
17 ADC1_DM1 ADC1_DM1
18 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
19 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
20 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
21 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
22 VDDA
VDDA
23 VREFH
VREFH
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
61