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K60P104M100SF2 Datasheet, PDF (25/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet | |||
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Peripheral operating requirements and behaviors
Table 12. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
tirefstf Internal reference startup time (fast clock)
â
TBD
TBD
µs
floc_low Loss of external clock minimum frequency â
RANGE = 00
(3/5) x
â
fints_t
â
kHz
floc_high Loss of external clock minimum frequency â
RANGE = 01, 10, or 11
(16/5) x
â
fints_t
â
kHz
FLL
fdco_t DCO output freâ
Low range (DRS=00)
20
quency range â
user trimmed
640 Ã fints_t
and DMX32=0
Mid range (DRS=01)
40
y 1280 Ã fints_t
Mid-high range (DRS=10
60
r 192)0 Ã fints_t
a High range (DRS=11)
80
2560 Ã fints_t
in fdco_t_DMX3 DCO output freâ
Low range (DRS=00)
â
2
quency range â
reference =
732 Ã fints_t
32,768Hz and
Mid range (DRS=01)
â
DMX32=1
1464 Ã fints_t
lim Mid-high range (DRS=10)
â
2197 Ã fints_t
High range (DRS=11)
â
2929 Ã fints_t
e Jcyc_fll FLL period jitter
â
r Jacc_fll FLL accumulated jitter of DCO output over a 1µs
â
time window
P tfll_acquire FLL target frequency acquisition time
â
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
TBD
TBD
â
25
50
75
100
â
â
â
â
TBD
TBD
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ms
PLL
fvco
VCO operating frequency
48.0
â
100
MHz
fpll_ref PLL reference frequency range
2.0
â
4.0
MHz
Jcyc_pll PLL period jitter
â
400
â
ps
Jacc_pll PLL accumulated jitter over 1µs window
â
TBD
â
ps
Dlock Lock entry frequency tolerance
± 1.49
â
± 2.98
%
Dunl Lock exit frequency tolerance
± 4.47
â
± 5.97
%
tpll_lock Lock detector detection time
â
â
0.15 +
ms
1075(1/
fpll_ref)
Notes
1, 2
3
4
5
6, 7
6,7
8
1. The resulting system clock frequencies should not exceed their maximum specified values.
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
25
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