K60P104M100SF2 Datasheet, PDF (53/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6.8.5 DSPI Switching Specifications for Low-speed Operation
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master Mode DSPI Timing (Low-speed mode)
Num
DS1
DS2
DS3
DS4
DS5
DS6
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
Min.
1.71
—
y ^{4 x t}BCLK
r ^{(tSCK/2) - 4}
(t_SCK/2) - 4
a (tSCK/2) - 4
—
in^-2
Max.
3.6
12.5
—
(t_SCK/2) + 4
—
—
10
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
Notes
1
DS7
DSPI_SIN to DSPI_SCK input setup
DS8
DSPI_SCK to DSPI_SIN input hold
15
—
ns
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
lim ^{range the maximum frequency of operation is reduced.}
DSPI_PCSn
e _{DSPI_SCK}
r _(CPOL=0)
P ^DSPI_SIN
DS3
DS7
DS8
First data
DS2
Data
DS5
DS1
DS4
Last data
DS6
DSPI_SOUT
First data
Data
Last data
Figure 20. DSPI Classic SPI Timing — Master Mode
Table 39. Slave Mode DSPI Timing (Low-speed Mode)
Num
DS9
Description
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
Min.
1.71
—
8 x t_BCLK
Max.
3.6
6.25
—
Unit
V
MHz
ns
Table continues on the next page...
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
53