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K60P104M100SF2 Datasheet, PDF (15/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet | |||
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5.1.4 Power mode transition operating behaviors
In the table below, all specifications except tPOR, assume the following clock
configuration:
⢠CPU and system clocks = 100MHz
⢠Bus and FlexBus clocks = 50 MHz
⢠Flash clock = 25 MHz
General
Symbol
tPOR
Table 4. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point VDD
â
300
μs
y reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
r RUN â VLLS1 â RUN
⢠RUN â VLLS1
â
4.1
μs
a ⢠VLLS1 â RUN
â
123.8
μs
RUN â VLLS2 â RUN
in ⢠RUN â VLLS2
⢠VLLS2 â RUN
â
4.1
μs
â
49.3
μs
RUN â VLLS3 â RUN
lim ⢠RUNâVLLS3
⢠VLLS3 â RUN
â
4.1
μs
â
49.2
μs
RUN â LLS â RUN
⢠RUN â LLS
e ⢠LLS â RUN
â
4.1
μs
â
5.9
μs
r RUN â STOP â RUN
P ⢠RUN â STOP
â
4.1
μs
⢠STOP â RUN
â
4.2
μs
Notes
1
RUN â VLPS â RUN
⢠RUN â VLPS
⢠VLPS â RUN
â
4.1
μs
â
5.8
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
15
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