K60P104M100SF2 Datasheet, PDF (51/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet

RXCLK (input)
RXD[n:0]
Peripheral operating requirements and behaviors
MII2
MII1
MII3
MII4
Valid data
RXDV
Valid data
RXER
Valid data
Figure 19. MII receive signal timing diagram
ry _{6.8.1.2 RMII signal switching specifications}
a The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
in ^{Table 35. Ethernet RMII mode signal timing}
Num
—
RMII1
RMII2
RMII3
RMII4
RMII7
RMII8
Description
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
lim ^{RMII_CLK pulse width low}
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
e _{RMII_CLK to RXD[1:0], CRS_DV, RXER hold}
r ^{RMII_CLK to TXD[1:0], TXEN invalid}
P ^{RMII_CLK to TXD[1:0], TXEN valid}
Min.
—
35%
35%
4
2
4
—
Max.
50
65%
65%
—
—
—
15
Unit
MHz
RMII_CLK
period
RMII_CLK
period
ns
ns
ns
ns
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
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