K60P104M100SF2 Datasheet, PDF (50/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6.8.1 Ethernet Switching Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII Signal Switching Specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 34. Ethernet MII mode signal timing
y _Symbol
r _—
MII1
Description
RXCLK frequency
RXCLK pulse width high
ina ^MII2
RXCLK pulse width low
Min.
—
35%
35%
Max.
25
65%
65%
Unit
MHz
RXCLK
period
RXCLK
period
MII3
MII4
—
MII5
MII6
MII7
MII8
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
lim ^{TXCLK pulse width high}
TXCLK pulse width low
e _{TXCLK to TXD[3:0], TXEN, TXER invalid}
Pr ^{TXCLK to TXD[3:0], TXEN, TXER valid}
5
5
—
35%
35%
2
—
—
—
25
65%
65%
—
25
ns
ns
MHz
TXCLK
period
TXCLK
period
ns
ns
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 18. MII transmit signal timing diagram
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
50
Preliminary
Freescale Semiconductor, Inc.