K60P104M100SF2 Datasheet, PDF (55/67 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 40. Master Mode DSPI Timing (High-speed mode) (continued)
Num
DS4
DS5
DS6
DS7
DS8
Description
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
Max.
Unit
(t_SCK/2) − 2
—
ns
—
8.5
ns
−2
—
ns
TBD
—
ns
0
—
ns
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS7
DS8
First data
DS2
DS5
First data
DS1
DS4
ry _Data
Last data
DS6
ina ^Data
Last data
Num
DS9
DS10
DS11
DS12
Figure 22. DSPI Classic SPI Timing — Master Mode
Table 41. Slave Mode DSPI Timing (High-speed mode)
lim ^{Operating voltage}
Description
Frequency of operation
DSPI_SCK input cycle time
e _{DSPI_SCK input high/low time}
r _{DSPI_SCK to DSPI_SOUT valid}
P ^{DSPI_SCK to DSPI_SOUT invalid}
Min.
2.7
4 x t_BCLK
(t_SCK/2) − 2
—
0
Max.
3.6
12.5
—
(t_SCK/2 + 2
TBD
—
Unit
V
MHz
ns
ns
ns
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
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