MSC8252 Datasheet, PDF (55/68 Pages) Freescale Semiconductor, Inc – orderDual-Core Digital Signal Processor

3.1.4 Reset Guidelines
When a debugger is not used, implement the connection scheme shown in Figure 35.
Hardware Design Considerations
On-board PORESET source
(example: voltage monitor)
MSC815x
TRST
PORESET
Figure 35. Reset Connection in Functional Application
When a debugger is used, implement the connection scheme shown in Figure 36.
VDD_IO
On-board TRST source
(example: OnCE)
10 ΚΩ
MSC815x
On-board PORESET source
(example: voltage monitor)
TRST
PORESET
Figure 36. Reset Connection in Debugger Application
3.2 PLL Power Supply Design Considerations
Each global PLL power supply must have an external RC filter for the PLLn_AVDD input (see Figure 37) in which the
following components are defined as listed:
• R = 5 Ω ± 5%
• C1 = 10 µF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH, low ESL Surface Mount Capacitor.
• C2 = 1.0 µF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH, low ESL Surface Mount Capacitor.
Note: A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change.
All three PLLs can connect to a single supply voltage source (such as a voltage regulator) as long as the external RC filter is
applied to each PLL separately. For optimal noise filtering, place the circuit as close as possible to its PLLn_AVDD inputs.
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
55