MSC8252 Datasheet, PDF (51/68 Pages) Freescale Semiconductor, Inc – orderDual-Core Digital Signal Processor

Figure 30 shows the boundary scan (JTAG) timing diagram.
TCK
(Input)
Data
Inputs
t_TCKHOV
t_BSVKH
t_BSXKH
Input Data Valid
Data
Outputs
t_TCKHOZ
Output Data Valid
Data
Outputs
Figure 30. Boundary Scan (JTAG) Timing
Figure 31 shows the test access port timing diagram.
TCK
(Input)
TDI
TMS
(Input)
t_TDOHOV
t_TDIVKH
t_TDIXKH
Input Data Valid
TDO
(Output)
t_TDOHOZ
Output Data Valid
TDO
(Output)
Figure 31. Test Access Port Timing
Figure 32 shows the TRST timing diagram.
TRST
(Input)
t_TRST
Figure 32. TRST Timing
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
51