MSC8252 Datasheet, PDF (52/68 Pages) Freescale Semiconductor, Inc – orderDual-Core Digital Signal Processor

Hardware Design Considerations
3 Hardware Design Considerations
The following sections discuss areas to consider when the MSC8252 device is designed into a system.
3.1 Power Supply Ramp-Up Sequence
The following subsections describe the required device initialization sequence.
3.1.1 Clock, Reset, and Supply Coordination
Starting the device requires coordination between several inputs including: clock, reset, and power supplies. Follow this
guidelines when starting up an MSC8252 device:
• PORESET and TRST must be asserted externally for the duration of the supply ramp-up, using the V_DDIO supply.
TRST deassertion does not have to be synchronized with PORESET deassertion. However, TRST must be deasserted
before normal operation begins to ensure correct functionality of the device.
• CLKIN should toggle at least 32 cycles before PORESET deassertion to guarantee correct device operation. The 32
cycles should only be counted from the time after V_DDIO reaches its nominal value (see timing 1 in Figure 33).
• CLKIN should either be stable low during ramp-up of V_DDIO supply (and start its swings after ramp-up) or should
swing within V_DDIO range during V_DDIO ramp-up, so its amplitude grows as V_DDIO grows during ramp-up.
Figure 33 shows a sequence in which V_DDIO ramps-up after V_DD and CLKIN begins to toggle with the raise of V_DDIO supply.
V_DDIO = Nominal
V_DD = Nominal
1
V_DDIO Nominal
V_DD Nominal
PORESET/TRST asserted
V_DD applied
CLKIN starts toggling
V_DDIO applied
Time
PORESET deasserted
Figure 33. Supply Ramp-Up Sequence with V_DD Ramping Before V_DDIO and CLKIN Starting With V_DDIO
Note: For details on power-on reset flow and duration, see the Reset chapter in the MSC8252 Reference Manual.
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3
52
Freescale Semiconductor