MSC8252 Datasheet, PDF (25/68 Pages) Freescale Semiconductor, Inc – orderDual-Core Digital Signal Processor

2.4 CLKIN Requirements
Table 5 summarizes the required characteristics for the CLKIN signal.
Table 5. CLKIN Requirements
Parameter/Condition¹
Symbol
Min
Typ
CLKIN duty cycle
—
40
—
CLKIN slew rate
—
1
—
CLKIN peak period jitter
—
—
—
CLKIN jitter phase noise at –56 dBc
—
—
—
AC input swing limits
ΔV_AC
1.5
—
Input capacitance
C_IN
—
—
Notes: 1. For clock frequencies, see the Clock chapter in the MSC8252 Reference Manual.
2. Measured at the rising edge and/or the falling edge at V_DDIO/2.
3. Slew rate as measured from ±20% to 80% of voltage swing at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
Electrical Characteristics
Max
60
4
±150
500
—
15
Unit
%
V/ns
ps
KHz
V
pf
Notes
2
3
—
4
—
—
2.5 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8252.
2.5.1 DDR SDRAM DC Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8252.
Note: DDR2 SDRAM uses V_DDDDR(typ) = 1.8 V and DDR3 SDRAM uses V_DDDDR(typ) = 1.5 V.
2.5.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 6 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM.
Note: At recommended operating conditions (see Table 3) with V_DDDDR = 1.8 V.
Table 6. DDR2 SDRAM Interface DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O reference voltage
MV_REF
0.49 × V_DDDDR
0.51 × V_DDDDR
V
2, 3, 4
Input high voltage
V_IH
MV_REF + 0.125
V_DDDDR + 0.3
V
5
Input low voltage
V_IL
–0.3
MV_REF – 0.125
V
5
I/O leakage current
I_OZ
–50
50
μA
6
Output high current (V_OUT (VOH) = 1.37 V)
I_OH
–13.4
—
mA
7
Output low current (V_OUT (VOL) = 0.33 V)
I_OL
13.4
—
mA
7
Notes: 1. V_DDDDR is expected to be within 50 mV of the DRAM V_DD supply voltage at all times. The DRAM and memory controller can
use the same or different sources.
2. MV_REF is expected to be equal to 0.5 × V_DDDDR, and to track V_DDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MV_REF may not exceed ±2% of the DC value.
3. V_TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal
to MV_REF with a minimum value of MV_REF – 0.4 and a maximum value of MV_REF + 0.04 V. V_TT should track variations in the
DC-level of MV_REF.
4. The voltage regulator for MV_REF must be able to supply up to 300 μA.
5. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
6. Output leakage is measured with all outputs are disabled, 0 V ≤ V_OUT ≤ V_DDDDR.
7. Refer to the IBIS model for the complete output IV curve characteristics.
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
25