MSC8252 Datasheet, PDF (2/68 Pages) Freescale Semiconductor, Inc – orderDual-Core Digital Signal Processor

Table of Contents
1 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagram. . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .24
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .24
2.4 CLKIN Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .25
2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .36
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .52
3.1 Power Supply Ramp-Up Sequence . . . . . . . . . . . . . . .52
3.2 PLL Power Supply Design Considerations . . . . . . . . . .55
3.3 Clock and Timing Signal Board Layout Considerations 56
3.4 SGMII AC-Coupled Serial Link Connection Example . .57
3.5 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .57
3.6 Guide to Selecting Connections for Remote Power
Supply Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
List of Figures
Figure 1. MSC8252 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC3850 DSP Subsystem Block Diagram . . . . 3
Figure 3. MSC8252 FC-PBGA Package, Top View . . . . . . . . . . . . 4
Figure 4. Differential Voltage Definitions for Transmitter or
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 29
Figure 6. SerDes Transmitter and Receiver Reference Circuits . 30
Figure 7. Differential Reference Clock Input DC Requirements
(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. Differential Reference Clock Input DC Requirements
(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9. Single-Ended Reference Clock Input DC Requirements 31
Figure 10.SGMII Transmitter DC Measurement Circuit . . . . . . . . 33
Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 39
Figure 14.DDR2 and DDR3 Controller Bus AC Test Load. . . . . . . 39
Figure 15.DDR2 and DDR3 SDRAM Differential Timing
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16.Differential Measurement Points for Rise and Fall Time 41
Figure 17.Single-Ended Measurement Points for Rise and Fall Time
Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 43
Figure 19.SGMII AC Test/Measurement Load. . . . . . . . . . . . . . . . 44
Figure 20.TDM Receive Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21.TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22.TDM AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 23.Timer AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . . 47
Figure 25.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 48
Figure 26.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 27.SPI AC Timing in Slave Mode (External Clock). . . . . . . 49
Figure 28.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 49
Figure 29.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 30.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 51
Figure 31.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 32.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 33.Supply Ramp-Up Sequence with V_DD Ramping Before
V_DDIO and CLKIN Starting With V_DDIO . . . . . . . . . . . . . 52
Figure 34.Supply Ramp-Up Sequence . . . . . . . . . . . . . . . . . . . . . 53
Figure 35.Reset Connection in Functional Application . . . . . . . . . 55
Figure 36.Reset Connection in Debugger Application. . . . . . . . . . 55
Figure 37.PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 38.SerDes PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 42.4-Wire AC-Coupled SGMII Serial Link Connection
Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 40.MSC8252 Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3
2
Freescale Semiconductor