MSC8252 Datasheet, PDF (44/68 Pages) Freescale Semiconductor, Inc – orderDual-Core Digital Signal Processor

Electrical Characteristics
2.6.2.4 SGMII AC Timing Specifications
Note: Specifications are valid at the recommended operating conditions listed in Table 3.
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) or at
the receiver inputs (SR[1–2]_RX[n] and SR[1–2]_RX[n]) as depicted in Figure 19, respectively.
D+ Package
Pin
TX
Silicon
+ Package
D– Package
Pin
C = C_TX
C = C_TX
R = 50 Ω
R = 50 Ω
Figure 19. SGMII AC Test/Measurement Load
Table 29 provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing
specifications do not include REF_CLK jitter.
Table 29. SGMII Transmit AC Timing Specifications
Parameter
Symbol
Min
Typ
Deterministic Jitter
Total Jitter
JD
—
—
JT
—
—
Unit Interval
UI
799.92
800
Notes: 1. See Figure 18 for single frequency sinusoidal jitter limits
2. Each UI is 800 ps ± 100 ppm.
Max
0.17
0.35
800.08
Unit
UI p-p
UI p-p
ps
Notes
—
2
1
Table 30 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include REF_CLK jitter.
Table 30. SGMII Receive AC Timing Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
0.37
—
—
UI p-p
1, 2
Combined Deterministic and Random Jitter Tolerance
JDR
0.55
—
—
UI p-p
1, 2
Total Jitter Tolerance
Bit Error Ratio
JT
BER
0.65
—
—
—
UI p-p
1,2
—
10^-12
—
—
Unit Interval
UI
799.92
800.00
800.08
ps
3
Notes: 1. Measured at receiver.
2. Refer to RapidIO^TM 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. Also see Figure 18.
3. Each UI is 800 ps ± 100 ppm.
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3
44
Freescale Semiconductor