DSP56853 Datasheet, PDF (49/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

56800E Core Description
• Address Generation Unit (AGU)
• Program controller and hardware looping unit
• Bit-manipulation unit
• Enhanced OnCE debugging module
• Clock generation
• Reset circuitry
1.4.5 Address Buses
The core contains three address buses:
1. Program memory Address Bus (PAB)
2. Primary Data Address Bus (XAB1)
3. Secondary Data Address Bus (XAB2)
The PAB is 21 bits wide. It is used to address (16-bit) words in program memory. The two 24-bit
data address buses permit two simultaneous accesses to data (X) memory. The XAB1 bus can
address byte, word, and long data types. The XAB2 bus is limited to (16-bit) word accesses.
All three buses address on- and off-chip memory on devices containing an external bus interface
unit. The 56857 device does not provide external addressing. The XAB2 can not go off-chip.
1.4.6 Data Buses
Data transfers inside the chip occur over the following buses:
• Two unidirectional 32-bit buses:
— Core Data Bus for Reads (CDBR)
— Core Data Bus for Writes (CDBW)
• Two unidirectional 16-bit buses:
— Secondary X Data Bus (XDB2)
— Program Data Bus (PDB)
• IPBus interface
Data transfers between the data ALU and data memory use the CDBR and CDBW when a single
memory read or write is performed. When two simultaneous memory reads are performed, the
transfers use the CDBR and XDB2 buses. All other data transfers to core blocks occur using the
CDBR and CDBW buses. Peripheral transfers occur through the IPBus interface. Instruction
word fetches occur over the PDB.
Freescale Semiconductor
5685X Overview, Rev. 4
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