DSP56853 Datasheet, PDF (345/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
12.8.9.5 Transmit DMA Enable (TDMAE)—Bit 11
This bit allows the ESSI to request a DMA transfer for the next data to transmit.
If the transmit FIFO is disabled:
• 0 = No DMA transfer is requested.
• 1 = A DMA request is generated when the ESSI Transmit Data Empty (TDE) bit is set.
If the transmit FIFO is enabled:
• 0 = No DMA transfer is requested.
• 1 = A DMA request is generated when the ESSI Transmit FIFO Empty (TFE) bit in the
SSR is set. The Transmit FIFO Empty Watermark bit can be set to any level. The FIFO is
then filled to the indicated level by the DMA controller so data is readily available in the
ESSI.
Transmit Interrupt Enable (TIE) has higher priority than Transmit DMA Enable (TDMAE). For
example, if TIE is set, an interrupt is generated to the CPU instead of DMA.
Note: If more than one transmit channel is enabled, a DMA channel is required for each
transmitter.
Note: If DMA is not supported on the chip, this bit has no meaning and should always be
cleared.
12.8.9.6 Receive Frame Sync Invert (RFSI)—Bit 10
This bit selects the logic of frame sync I/O for the receive section.
• 0 = Frame sync is active high.
• 1 = Frame sync is active low.
12.8.9.7 Receive Frame Sync Length (RFSL)—Bit 9
This bit selects the length of the frame sync signal to be generated or recognized for the receive
section.
Please note the first portion of Figure 12-21 for an example timing diagram of the frame sync
options.
• 0 = A one-word long frame sync is selected. The length of a word-long frame sync is the
same as the length of the data word selected by WL.
• 1 = A one-bit long frame sync is selected.
Freescale Semiconductor
Enhanced Synchronous Serial Interface (ESSI), Rev. 4
12-45