DSP56853 Datasheet, PDF (292/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

SPI Register Descriptions (SPI_BASE = $1FFFE8)
11.11 SPI Register Descriptions (SPI_BASE = $1FFFE8)
Table 11-3 lists the SPI registers in ascending address, including the acronym, bit names, and
address of each register. These read/write registers should be accessed only with word accesses.
Accesses other than word lengths result in undefined results.
11.11.1 SPI Status and Control Register (SPSCR)
The SPSCR register:
• Enables SPI module interrupt requests
• Selects interrupt requests
• Configures the SPI module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI module Receive Data register full interrupt
• Enables Transmits Data register empty interrupt
• Selects Master SPI baud rate
Base + $0
Read
Write
Reset
15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
SPR
SPRF OVRF MODF SPTE
DSO ERRIE MODFEN SPRIE SPMSTR CPOL CPHA SPE SPTIE
011 0
0
0
0
1
0
1
0
0
0
0
0
0
Note:
Figure 11-14. SPI Status and Control Register (SPSCR)
See Programmer’s Sheets on Appendix page B-64
Using BFCLR or BFSET instructions to modify SPSCR can cause unintended side
effects on the status bits.
11.11.1.1 SPI Baud Rate Select Bits (SPR)—Bits 15–13
While in the Master mode, these read/write bits select one of eight baud rates depicted in Table
11-4. SPR2:0 have no effect in Slave mode. Reset clears SPR2:0 to b011. Use the formula below
to calculate the SPI baud rate.
SPR1 and SPR0 have no effect in Slave mode. Reset clears SPR1 and SPR0. Use the formula
below to calculate the SPI baud rate.
Baud Rate =
CLK
BD
CLK = Peripheral Bus Clock BD = Baud Rate Divisor
11-22
5685X Digital Signal Controller User Manual, Rev. 4
Freescale Semiconductor