DSP56853 Datasheet, PDF (438/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

DSC Side Registers
16.8.1.4 DSC Side Transmit DMA Enable (TDMAEN)—Bit 6
The TDMAEN bit is used to enable DSC Side Transmit DMA operations. When this bit is set,
the on-chip DMA controller handles transferring data between the HTX register and DSC
memory. The on-chip DMA controller must be appropriately configured to implement the
desired data transfer.
16.8.1.5 DSC Side Receive DMA Enable (RDMAEN)—Bit 5
The RDMAEN bit is used to enable DSC Side Receive DMA operations. When this bit is set, the
on-chip DMA controller handles transferring data between the HRX register and DSC memory.
The on-chip DMA controller must be appropriately configured to implement the desired data
transfer.
16.8.1.6 Host Flags 2 and 3 (HF2–HF3)—Bits 4–3
The Host Flag 2 and Host Flag 3 (HF2 and HF3) bits are used as general purpose flags for
DSC-to-Host communication. HF2 and HF3 may be set or cleared by the core. HF2 and HF3 are
reflected in the Interrupt Status Register (ISR) on the Host Side if they are modified by the DSC
software, the Host Processor can read the modified values by reading the ISR.
These two flags are not designated for any specific purpose but are general purpose flags. They
can be used individually or as encoded pairs in a simple DSC-to-Host communication protocol,
implemented in both the DSC and the Host Processor software.
16.8.1.7 Host Command Interrupt Enable (HCIE)—Bit 2
The Host Command Interrupt Enable (HCIE) bit is used to enable a DSC core interrupt when the
HCP status bit in the HSR is set. When the HCIE bit is cleared, HCP interrupts are disabled.
When the HCIE bit is set, a Host Command Interrupt request occurs if HCP is set. The interrupt
address is determined by the Host Command Vector Register (CVR). The HCIE is cleared on
hardware reset.
Note:
Host interrupt request priorities: If more than one interrupt request source is asserted
and enabled (i.e., HRDF = 1, HCP = 1, HRIE = 1, and HCIE = 1) the HI8 generates
interrupt requests according to Table 16-5.
Table 16-5. HI8 Interrupt Request Order
Priority
Highest
—
Lowest
Interrupt Source
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Receive Data (HRDF = 1)
16-12
5685X Digital Signal Controller User Manual, Rev. 4
Freescale Semiconductor