DSP56853 Datasheet, PDF (43/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

5685x Family Architectural Overview
Memory
Program Memory
40,960 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
6
JTAG/
Enhanced
OnCE
V_DDIO
12
V_DD VSSIO VSS VDDA VSSA
8
14 8
2
16-Bit
56800E Core
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System
Bus
Control
DMA
6 channel
IPBus Bridge (IPBB)
A0-20 [20:0]
D0-D15 [15:0]
RD Enable
WR Enable
CS0-CS3[3:0] or
GPIOA0-A3
Decoding
Peripherals
External Address
Bus Switch
External Data External Bus
Bus Switch Interface Unit
Bus Control
2 SCI ESSI0
or
or
GPIOE GPIOC
ESSI1
or
GPIOD
Quad
Timer
or
GPIOG
SPI
or
GPIOF
Host Interrupt
Interface Controller
or
GPIOB
4
6
6
4
4
16 _IRQA
IRQB
COP/
Watch-
dog
POR
CLKO
IPBus CLK
3
MODE A-C or
System
GPIOH0-H2
COP/TOD CLK Integration
Module
RSTO
RESET
Time
of
Day
Clock
Generator
OSC PLL
EXTAL
XTAL
Figure 1-5. 56858 Functional Block Diagram
Freescale Semiconductor
5685X Overview, Rev. 4
1-11