DSP56853 Datasheet, PDF (140/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

Timing Specifications
5.7 Timing Specifications
5.7.1 Read Timing
5.7.1.1 Consecutive Mode Operation
Figure 5-8 illustrates the read timing for external memory access. For comparison, a single read
cycle is illustrated followed by a null cycle and then a back-to-back read.
Figure 5-8 assumes zero wait states are required for the access. Figure 5-9 illustrates a timing
diagram with one wait state added.
There are two read setup timing parameters for each read cycle. The core will latch the data on
the rising edge of the internal clock while t_RSD indicates the core setup time. The external timing
of the address and controls is adjusted so they may be changing at this time. Therefore, a data
latch is introduced to capture the data (at the pin) a quarter clock earlier, on the rising edge of the
internal delayed clock. The setup time required for this latch is illustrated by t_RSDP in the
diagrams. For slow clock speeds, t_RSDP is more critical, while t_RSD may be harder to meet for
faster clock rates.
Note: During back-to-back reads, RD remains low to provide the fastest read cycle time.
int_sys_clk
int_sys_clk_delay
A[23:0]
CS[7:0]
Read (RWS = 0)
t_C
IDLE
Read (RWS = 0) Read (RWS = 0)
t_RC
t_AV
t_CSV
t_AV
t_CSRH
t_CLKA
RD, OE
WR
t_RL
t_RH
t_RSDP
D[15:0]
t_RSD
t_OEV
t_ACCESS
Data In
t_RHD
t_OHZ
t_RSD
t_RSDP
Data In
t_RSDP
t_RSD
t_ACCESS
Data In
Figure 5-8. External Read Cycle with Clock and RWS = 0
5-14
5685X Digital Signal Controller User Manual, Rev. 4
Freescale Semiconductor