DSP56853 Datasheet, PDF (190/662 Pages) Freescale Semiconductor, Inc – Digitial Signal Controller

Register Descriptions (ITCN_BASE = $1FFF20)
8.7.4 Interrupt Priority Register 3 (IPR3)
Base + $3
Read
Write
Reset
15 14 13 12 11 10
ESS0_TD ESS0_TDES ESS0_RLS
IPL
IPL
IPL
0
0
0
0
0
0
9
8
ESS0_RD
IPL
0
0
7
6
ESS0_RDE
S IPL
0
0
5
4
DMA5 IPL
0
0
3
2
DMA4 IPL
0
0
1
0
DMA3 IPL
0
0
Figure 8-6. Interrupt Priority Register 3 (IPR3)
See Programmer’s Sheet on Appendix page B - 25
8.7.4.1 ESSI0 Transmit Data Interrupt Priority Level
(ESSI0_TD IPL)—Bits 15–14
This bit field is used to set the interrupt priority levels for certain peripheral IRQs. These IRQs
are limited to priorities zero through two and are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
8.7.4.2 ESSI0 Transmit Data with Exception Status Interrupt Priority Level
(ESSI0_TDES IPL)—Bits 13–12
This bit field is used to set the interrupt priority levels for certain peripheral IRQs. These IRQs
are limited to priorities zero through two and are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
8.7.4.3 ESSI0 Receive Last Slot Interrupt Priority Level
(ESSI0_RLS IPL)—Bits 11–10
This bit field is used to set the interrupt priority levels for certain peripheral IRQs. These IRQs
are limited to priorities zero through two and are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
8-12
5685X Digital Signal Controller User Manual, Rev. 4
Freescale Semiconductor