K30P64M72SF1 Datasheet, PDF (43/68 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
G
Description
Gain⁴
Conditions
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
Min.
Typ.¹
Max.
Unit
Notes
0.95
1
1.05
1.9
2
2.1
R_AS < 100Ω
3.8
4
4.2
7.6
8
8.4
15.2
16
16.6
30.0
31.6
33.2
58.8
63.3
67.8
BW
PSRR
Input signal
bandwidth
Power supply
rejection ratio
• 16-bit modes
• < 16-bit modes
Gain=1
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
V_OFS
Input offset
voltage
T_GSW
Gain switching
settling time
dG/dT
Gain drift over full
temperature
range
dG/dV_DDA Gain drift over
supply voltage
• Gain=1
• Gain=64
• Gain=1
• Gain=64
E_IL
Input leakage
All modes
error
V_PP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
• Gain=1
• Gain=64
—
—
4
kHz
—
—
40
kHz
—
-84
—
dB
V_DDA= 3V
±100mV,
f_VDDA= 50Hz,
60Hz
—
-84
—
dB
V_CM=
—
-85
—
dB
500mVpp,
f_VCM= 50Hz,
100Hz
—
0.2
—
mV Output offset =
V_OFS*(Gain+1)
—
—
10
µs
5
—
6
10
ppm/°C
—
31
42
ppm/°C
—
0.07
0.21
—
0.14
0.31
I_In × R_AS
%/V V_DDA from 1.71
%/V
to 3.6V
mV
I_In = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
V
6
where V_X = V_REFPGA × 0.583
80
90
—
dB
52
66
—
dB
16-bit
differential
mode,
Average=32
Table continues on the next page...
K30 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
43